Detecting 1'bx and 1'bz bits in a Verilog variable

Detecting 1'bx and 1'bz bits in a Verilog variable

I have a 128 bit wire:
wire [127:0] test;
I want to stop simulation if any of the bits of test is 1'bx or 1'bz. This is what I tried:
if(&test == 1'bx || &test == 1'bz) begin
   $stop;
end
Unfortunately, 1'bx and 1'bz do not seem to propagate under &. I have also tried replacing &test with |test.
How can I quickly check if test contains any "don't care" or "tristate" bits?